1. Field of the Invention
The present invention relates to a two-line transmission interface. More particularly, the present invention relates to a method for initializing a memory device having a two-line transmission interface.
2. Description of Related Art
Generally, in a two-line transmission interface, for example, an inter-integrated circuit bus (I2C BUS), two lines of a serial clock (SCL) line and a serial data (SDA) line are used to transmit data. Taking a liquid crystal display (LCD) as an example, a timing controller thereof can use the I2C BUS to access an electrically erasable programmable read-only memory (EEPROM). The timing controller provides the SCL to the EEPROM to synchronize a mutual communication timing. Data transmission between the timing controller and the EEPROM is only depended on one bus line of SDA. The timing controller has to access related set data in the EEPROM through the I2C BUS.
FIG. 1 is a diagram illustrating a read operation performed to the EEPROM by the timing controller through the I2C BUS. The timing controller provides the SCL to the EEPROM. The timing controller transmits a read request to the EEPROM through the SDA line according to SCL timing. After the read request is received, the EEPROM transmits corresponding data to the timing controller through the SDA line according to the SCL timing provided by the timing controller.
Referring to FIG. 1, the timing controller sends a start signal S to the EEPROM through the SDA line, so that the EEPROM enters a state for receiving a control byte. Then, the timing controller immediately sends the control byte containing an identification code and a read/write command to the EEPROM. Assuming an identification code of the EEPROM is 001, and the timing controller is about to write a target address in the EEPROM, the timing controller may transmit a control byte with a content of “1010 001 0” to the EEPROM, wherein the last bit “0” represents a “write” command. After the operation of receiving the control byte is completed through 8 clock cycles, the EEPROM immediately sends an acknowledgement signal ACK (i.e. logic 0) to the timing controller through the SDA line. After the timing controller receives the acknowledgement signal ACK, the timing controller writes the data (i.e. the aforementioned target address) into the EEPROM through the SDA line. After the operation of receiving the target address is completed through 8 clock cycles, the EEPROM immediately sends the acknowledgement signal ACK to the timing controller. Now, addressing operation of the EEPROM is completed.
The timing controller further transmits the start signal S to the EEPROM through the SDA, so that the EEPROM again enters the state for receiving the control byte. Then, the timing controller immediately sends the control byte to the EEPROM. Since a read operation is performed to the EEPROM, the timing controller transmits the control byte with a content of “1010 001 1” to the EEPROM, wherein the last bit “1” represents a “read” command. After the operation of receiving the control byte is completed through 8 clock cycles, the EEPROM immediately sends the acknowledgement signal ACK to the timing controller through the SDA line. Then, corresponding data of the above addressing operation is transmitted back to the timing controller through 8 clock cycles. After the data is transmitted back, the EEPROM immediately sends a signal NO_ACK to the timing controller. Finally, the timing controller sends a stop signal P to the EEPROM through the SDA line to trigger the EEPROM entering an initialization state (i.e. a state waiting for receiving a command of a main device). Now, the timing controller completes the read operation of the EEPROM.
However, in the above read operation, the read operation of the EEPROM performed by the timing controller can be interrupted by a glitch of a reset signal or other factors, and when the timing controller re-performs the read operation to the EEPROM, since the EEPROM is probably stopped at an undominative state due to the former interruption of the read operation, the timing controller cannot re-perform the read operation. Therefore, before the timing controller performs the read operation to the EEPROM, the EEPROM has to be initialized.